There is a trend for driving semiconductor devices with lower voltages to decrease power consumption. However, there are still semiconductor devices that are not driven by lower voltages and semiconductor devices of which drive voltages may not be lowered. As a result, recent semiconductor devices are provided with an interface that is applicable for external semiconductor devices actuated by different power supply voltages. Such a semiconductor device includes an output buffer circuit that switches a signal to different potentials in accordance with an operational power supply voltage of the external semiconductor device (refer to, for example, Japanese Laid-Open Patent Publication No. 6-343034).
FIG. 1 illustrates one example of an output buffer circuit 2 of the related art.
The output buffer circuit 2 includes a first output circuit 80, which outputs a signal with a first high potential power supply VDD1, and a second output circuit 90, which outputs a signal with a second high potential power supply VDD2. The voltage of the second high potential power supply VDD2 is lower than the voltage of the first high potential power supply VDD1. An output terminal of the first output circuit 80 and an output terminal of the second output circuit 90 are coupled to an output terminal To.
The first output circuit 80 includes a buffer circuit 81, which operates with the first high potential power supply VDD1, and an output driver 82, which is driven by the buffer circuit 81. In the first output circuit 80, when a control signal SEL has an L level, the output driver 82 activates one of output transistors T81 and T82 in accordance with the level of a signal Do to output a signal having the level of the first high potential power supply VDD1 or the level of a lower potential power supply VSS. When the control signal SEL has an H level, the output driver 82 deactivates both of the output transistors T81 and T82 to place an output node N1A between the output transistors T81 and T82 in a high impedance state.
The second output circuit 90 includes a buffer circuit 91, which operates with the first high potential power supply VDD1, and an output driver 92, which is driven by the buffer circuit 91. In the second output circuit 90, when the control signal SEL has an H level, the output driver 92 activates one of output transistors T91 and T92 in accordance with the level of the signal Do to output a signal having the level of the second high potential power supply VDD2, which is lower than the level of the first high potential power supply VDD1, or the level of a lower potential power supply VSS. When the control signal SEL has an L level, the output driver 92 deactivates both of the output transistors T91 and T92 to place an output node N2A between the output transistors T91 and T92 in a high impedance state.
When the output node N2A is in a high impedance state, the back gate voltage and gate voltage of the output transistor T91 are set at the level of the first high potential power supply VDD1 so that current does not flow to the output transistor T91. For example, when an output signal of the first output circuit 80 has the level of the first high potential power supply VDD1, since the output terminals of the first and second output circuits 80 and 90 are coupled to the output terminal To, the output signal of the first output circuit 80 is applied to the drains of the output transistors T91 and T92 of the second output circuit 90. In this state, when the back gate of the output transistor T91, which is a P-channel MOS transistor, is coupled to, for example, the second high potential power supply VDD2, the potential at the back gate becomes lower than the potential at the drain. This forms a diode in a forward direction from the drain to the back gate, and current flows to the output transistor T91. Thus, the level of the signal having the highest potential output to the output terminal To (here, the level of the first high potential power supply VDD1) is set as the back gate voltage of the output transistor T91. This prevents current from flowing to the output transistor T91 when the output node N2A is in a high impedance state.
When a signal having the level of the first high potential power supply VDD1 is output from the first output circuit 80 and a signal having the level of the second high potential power supply VDD2 is supplied to the gate of the output transistor T91, the output transistor T91 is activated by the relationship of the potentials at the source, drain, and gate of the output transistor T91. As a result, current flows from the first high potential power supply VDD1 via the output transistor T91 to the second high potential power supply VDD2. Thus, the operational power for the buffer circuit 91 of the second output circuit 90 is set to the first high potential power supply VDD1, and the gate of the output transistor T91 is provided with a signal having the level of the first high potential power supply VDD1. This prevents current from flowing to the output transistor T91 when the output node N2A is in a high impedance state.
However, the second high potential power supply VDD2 may be activated before the first high potential power supply VDD1. In such a case, the first high potential power supply VDD1 is deactivated. Thus, the back gate voltage and gate voltage of the output transistor T91 are not controlled as described above. Namely, the first high potential power supply VDD1 is 0 V. Thus, the gate of the output transistor T91 is provided with a signal having an L level. In this state, the source of the output transistor T91 is coupled to the second high potential power supply VDD2. Thus, the output transistor T91 is activated. This applies a signal having the level of the second high potential power supply VDD2 to the drain of the output transistor T81. At the same time, the gate of the output transistor T81 is provided with a signal having an L level. Thus, the output transistor T81 is also activated. As a result, inflow current flows from the second high potential power supply VDD2 to the first high potential power supply VDD1 (the first high potential power supply VDD1 coupled to the back gate of the output transistor T91 and the first high potential power supply VDD1 coupled to the source of the output transistor T81). This changes the power supply voltage.